This application claims the priority benefit of Taiwan application serial no. 90106705, filed on Mar. 22, 2001.
1. Field of the Invention
The invention relates to a wafer-level packaging process. More particularly, the invention relates to a wafer-level packaging process which uses a stress buffer layer instead of an underfill on the wafer.
2. Description of the Related Art
As electronic technology progresses, emphasis is more particularly focused on the miniaturization of electronic products. This miniaturization results in electronic products that are more complicated and denser. In the electronics industry, package structures that have small dimensions and high density are required for packaging of electronic devices. Many types of packages have been developed such as ball grid array (BGA) packages, chip-scale packages (CSP), flip-chip (F/C) packages, and multi-chip module (MCM) packages.
Among the above-mentioned types of packages, the flip-chip package provides many advantages, such as small surface area of the package, high pin count, short signal path, low induction and easy control of noise signals. Thus, the flip-chip structure is increasingly used in packaging electronic devices.
In a conventional flip-chip package, an underfill must be formed between the chip and the carrier or printed circuit substrate onto which the chip is connected. The underfill is directed to share the thermal stress generated between the carrier and the chip due to their different coefficients of thermal expansion, such that the bumps that electrically connect the chip to the carrier can be substantially prevented from fatigue due to thermal cycle.
With the increased integration of packaging, the pitch between the bumps formed on the chip is constantly being reduced. For a flip-chip package, an effective filling of underfill, without voids, thus becomes problematic and increases the manufacturing cost. Solutions that can overcome the above-described problems to allow for a reliable flip-chip structure are thus needed.
It is one object of the present invention is to provide a wafer-level packaging process in which a stress buffer layer is adequately formed on the wafer to substitute for an underfill in a conventional packaging process such that the wafer-level packaging can be simply achieved.
To achieve the foregoing and other objects, the present invention provides a wafer-level packaging process, comprising: providing a wafer that has a plurality of chips formed thereon, each of the chips having a plurality of bonding pads exposed through a passivation layer formed on the surface of the wafer; respectivelyforming an under ball metallurgy (UBM) on each bonding pad; forming a patterned photoresist over the wafer to define a plurality of scribe lines and a plurality of bump forming locations; forming a stress buffer layer in the regions not covered by the patterned photoresist over the wafer; removing the patterned photoresist; applying a stencil having a plurality of openings to the stress buffer layer and the scribe lines, such that the openings expose the bump forming locations; filling a solder material in the openings; removing the stencil; and performing a reflow process to form the bumps at the bump forming locations.
Further, the present invention also provides a wafer-level packaging process comprising: providing a wafer that has a plurality of chips formed thereon, each of the chips having a plurality of bonding pads exposed through a passivation layer formed on the surface of the wafer; forming a first patterned photoresist over the wafer to define a plurality of scribe lines and a plurality of bump forming locations; forming a stress buffer layer in the regions not covered by the first patterned photoresist over the wafer; removing the first patterned photoresist defining a plurality of first openings in the stress buffer layer corresponding to the locations of the bonding pads; forming a UBM on each bonding pad exposed through each first opening, wherein the UBM covers the bonding pad, the sidewalls of the first opening, and overlaps over the stress buffer layer; forming a second patterned photoresist having a plurality of second openings on the stress buffer layer and scribe lines, such that the second openings expose the first openings; filling a solder material in the first and second openings; performing a reflow process to form the bumps; and removing the second patterned photoresist.
After the above-described packaging process, the wafer is diced and is connected onto a carrier by flip chip interconnection technology. With the stress buffer layer substituting for the conventional underfill, the flip-chip package is thus simply obtained with a substantially reduced production cost.
It should be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.